# Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.04
# 08/31/2026 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.
CODE	UMASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	PEBS_COUNTER	OVERFLOW	MSR_INDEX	MSR_VALUE	PRECISE_EVENT	COLLECT_PEBS_DEFAULT	TAKEN_ALONE	SAV_LOWER_LIMIT	OTHER	LATENCY	DEFAULT	EM_TRIGGER	DATA_LA	L1_HIT_INDICATION	WORKAROUND	BRANCH_EVT	OFFMODULE	EQUAL	PDIST_COUNTER	EVENT_STATUS
0x00	0x01	0x00	INST_RETIRED.ANY	Fixed Counter: Counts the number of instructions retired.	32	32	2000003	0x00	0x00	1	2	0	5	0x53	0	1	1	0	0	0	0	0	0	32	0x00
0x00	0x02	0x00	CPU_CLK_UNHALTED.CORE	Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD]	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x00	0x02	0x00	CPU_CLK_UNHALTED.THREAD	Fixed Counter: Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE]	33	33	2000003	0x00	0x00	0	2	0	5	0x53	0	1	1	0	0	0	0	0	0	NA	0x00
0x00	0x03	0x00	CPU_CLK_UNHALTED.REF_TSC	Fixed Counter: Counts the number of unhalted reference clock cycles.	34	34	2000003	0x00	0x00	0	2	0	5	0x53	0	1	2	0	0	0	0	0	0	NA	0x00
0x00	0x05	0x00	TOPDOWN_BAD_SPECULATION.ALL	Fixed Counter: Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.	36	36	1000003	0x00	0x00	0	2	0	0	0x53	0	1	0	0	0	0	0	0	0	NA	0x00
0x00	0x06	0x00	TOPDOWN_FE_BOUND.ALL	Fixed Counter: Counts the number of retirement slots not consumed due to front end stalls.	37	37	1000003	0x00	0x00	0	2	0	0	0x53	0	1	0	0	0	0	0	0	0	NA	0x00
0x00	0x07	0x00	TOPDOWN_RETIRING.ALL	Fixed Counter: Counts the number of consumed retirement slots.	38	38	1000003	0x00	0x00	1	2	0	0	0x53	0	1	0	0	0	0	0	0	0	NA	0x00
0x03	0x01	0x00	LD_BLOCKS.DATA_UNKNOWN	Counts the number of retired loads that are blocked because its address exactly matches an older store whose data is not ready.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0x03	0x02	0x00	LD_BLOCKS.STORE_FORWARD	Counts the number of retired loads that are blocked because its address partially overlapped with an older store.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0x03	0x04	0x00	LD_BLOCKS.ADDRESS_ALIAS	Counts the number of retired loads that are blocked because it initially appears to be store forward blocked, but subsequently is shown not to be blocked based on 4K alias check.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0x03	0x08	0x00	LD_BLOCKS.DTLB_MISS	Counts the number of retired loads that are blocked due to a first level TLB miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0x03	0x1f	0x00	LD_BLOCKS.ALL	Counts the number of retired loads that are blocked for any of the following reasons:  DTLB miss, address alias, store forward or data unknown (includes memory disambiguation blocks and ESP consuming load blocks), and others.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0x05	0x01	0x00	LD_HEAD.L1_MISS	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DL1 miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x02	0x00	LD_HEAD.WCB_FULL	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to request buffers full or lock in progress.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x04	0x00	LD_HEAD.ST_ADDR	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a store address match.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x10	0x00	LD_HEAD.DTLB_MISS	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a DTLB miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x20	0x00	LD_HEAD.PGWALK	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a pagewalk.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x40	0x00	LD_HEAD.OTHER	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to other block cases.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x7f	0x00	LD_HEAD.ANY	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x81	0x00	LD_HEAD.L1_MISS_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DL1 miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x82	0x00	LD_HEAD.WCB_FULL_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to request buffers full or lock in progress.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x84	0x00	LD_HEAD.ST_ADDR_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a store address match.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0x90	0x00	LD_HEAD.DTLB_MISS_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xa0	0x00	LD_HEAD.PGWALK_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a pagewalk.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xc0	0x00	LD_HEAD.OTHER_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to other block cases.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xf4	0x00	LD_HEAD.L1_BOUND_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to a core bound stall including a store address match, a DTLB miss or a page walk that detains the load from retiring.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x05	0xff	0x00	LD_HEAD.ANY_AT_RET	Counts the number of cycles that the head (oldest load) of the load buffer is stalled due to any number of reasons, including an L1 miss, WCB full, pagewalk, store address block or store data block, on a load that retires.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x01	0x00	DTLB_LOAD_MISSES.MISS_CAUSED_WALK	Counts the number of page walks initiated by a demand load that missed the first and second level TLBs.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x02	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED_4K	Counts the number of page walks completed due to load DTLB misses to a 4K page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x04	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M	Counts the number of page walks completed due to load DTLB misses to a 2M or 4M page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x08	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED_1G	Counts the number of page walks completed due to load DTLB misses to a 1G page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x0e	0x00	DTLB_LOAD_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to load DTLB misses to any page size.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x10	0x00	DTLB_LOAD_MISSES.WALK_PENDING	Counts the number of page walks outstanding for Loads (demand or SW prefetch) in PMH every cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x20	0x00	DTLB_LOAD_MISSES.STLB_HIT_4K	Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for 4k page size only. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x40	0x00	DTLB_LOAD_MISSES.STLB_HIT_LGPG	Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Account for large page sizes only. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x60	0x00	DTLB_LOAD_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to a demand load that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x08	0x80	0x00	DTLB_LOAD_MISSES.PDE_CACHE_MISS	Counts the number of page walks due to loads that miss the PDE (Page Directory Entry) cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x0e	0x00	0x00	UOPS_ISSUED.ANY	Counts the number of uops issued by the front end every cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x26	0x04	0x00	L2_LINES_OUT.USELESS_HWPF	Counts the number of L2 cache lines that have been L2 hardware prefetched but not used by demand accesses.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x2e	0x41	0x00	LONGEST_LAT_CACHE.MISS	Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x2e	0x4f	0x00	LONGEST_LAT_CACHE.REFERENCE	Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x30	0x00	0x00	L2_REJECT_XQ.ANY	Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x31	0x00	0x00	CORE_REJECT_L2Q.ANY	Counts the number of requests that were not accepted into the L2Q because the L2Q is FULL.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x01	0x00	MEM_BOUND_STALLS_LOAD.L2_HIT_LOCAL_MODULE	Counts the number of unhalted cycles when the core is stalled due to L1 cache miss. that hit the L2 cache within the same module.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x02	0x00	MEM_BOUND_STALLS_LOAD.CACHE_HIT_LOCAL_CBB	Counts the number of unhalted cycles when the core is stalled due to L1 cache miss that hit an L2 in different module, L3, or MMIO, on the same CBB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x06	0x00	MEM_BOUND_STALLS_LOAD.LLC_CACHE_HIT	Counts the number of unhalted cycles when the core is stalled due to L1cache miss that hit in any cache, L2 or L3 or MMIO, that is not on the same CBB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x10	0x00	MEM_BOUND_STALLS_LOAD.MEM_HIT_LOCAL_SOCKET	Counts the number of unhalted cycles when the core is stalled due to L1 cache miss that hit in memory regions 0, 1, 2, 4, 5.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x30	0x00	MEM_BOUND_STALLS_LOAD.MEM_HIT_ANY_SOCKET	Counts the number of unhalted cycles when the core is stalled due to a load miss at ret that hit in memory regions 0, 1, 2, 3, 4, 5, 6, 7.  Memory regions may be mapped to the local or remote sockets.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x3c	0x00	MEM_BOUND_STALLS_LOAD.CACHE_MISS_LOCAL_CBB	Counts the number of unhalted cycles when the core is stalled due to L1 cache miss that also miss an L2 in different module, L3, or MMIO, on the same CBB	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x3e	0x00	MEM_BOUND_STALLS_LOAD.L2_MISS_LOCAL_MODULE	Counts the number of unhalted cycles when the core is stalled due to L1 cache miss. that miss the L2 cache within the same module.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x34	0x3f	0x00	MEM_BOUND_STALLS_LOAD.ALL	Counts the number of unhalted cycles when the core is stalled due to L1 cache miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x3c	0x00	0x00	CPU_CLK_UNHALTED.CORE_P	Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x3c	0x00	0x00	CPU_CLK_UNHALTED.THREAD_P	Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	1	0	0	0	0	0	0	NA	0x00
0x3c	0x01	0x00	CPU_CLK_UNHALTED.REF_TSC_P	Counts the number of unhalted reference clock cycles at TSC frequency.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	0	2	0	5	0x53	0	0	3	0	0	0	0	0	0	NA	0x00
0x49	0x01	0x00	DTLB_STORE_MISSES.MISS_CAUSED_WALK	Counts the number of page walks initiated by a store that missed the first and second level TLBs.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x02	0x00	DTLB_STORE_MISSES.WALK_COMPLETED_4K	Counts the number of page walks completed due to store DTLB misses to a 4K page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x04	0x00	DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M	Counts the number of page walks completed due to store DTLB misses to a 2M or 4M page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x08	0x00	DTLB_STORE_MISSES.WALK_COMPLETED_1G	Counts the number of page walks completed due to store DTLB misses to a 1G page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x0e	0x00	DTLB_STORE_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to store DTLB misses to any page size.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x10	0x00	DTLB_STORE_MISSES.WALK_PENDING	Counts the number of page walks outstanding in the page miss handler (PMH) for stores every cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x20	0x00	DTLB_STORE_MISSES.STLB_HIT_4K	Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for 4k page size only. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x40	0x00	DTLB_STORE_MISSES.STLB_HIT_LGPG	Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Account for large page sizes only. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x60	0x00	DTLB_STORE_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to stores that did not start a page walk. Accounts for all page sizes. Will result in a DTLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x49	0x80	0x00	DTLB_STORE_MISSES.PDE_CACHE_MISS	Counts walks that miss the PDE_CACHE.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x01	0x00	TOPDOWN_FE_BOUND.CISC	Counts the number of issue slots every cycle that were not delivered by the frontend due to MS.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x02	0x00	TOPDOWN_FE_BOUND.BRANCH_DETECT	Counts the number of issue slots every cycle that were not delivered by the frontend due to BAClear.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x04	0x00	TOPDOWN_FE_BOUND.PREDECODE	Counts the number of issue slots every cycle that were not delivered by the frontend due to predecode wrong.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x08	0x00	TOPDOWN_FE_BOUND.DECODE	Counts the number of issue slots every cycle that were not delivered by the frontend due to decode stall.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x10	0x00	TOPDOWN_FE_BOUND.ITLB_MISS	Counts the number of issue slots every cycle that were not delivered by the frontend due to ITLB miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x20	0x00	TOPDOWN_FE_BOUND.ICACHE	Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x40	0x00	TOPDOWN_FE_BOUND.BRANCH_RESTEER	Counts the number of issue slots every cycle that were not delivered by the frontend due to BTClear.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x72	0x00	TOPDOWN_FE_BOUND.FRONTEND_LATENCY	Counts the number of issue slots every cycle that were not delivered by the frontend due to latency related stalls including BACLEARs, BTCLEARs, ITLB misses, and ICache misses.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x71	0x80	0x00	TOPDOWN_FE_BOUND.OTHER	Counts the number of issue slots every cycle that were not delivered by the frontend that do not categorize into any other common frontend stall.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x00	0x00	TOPDOWN_BAD_SPECULATION.ALL_P	Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x01	0x00	TOPDOWN_BAD_SPECULATION.NUKE	Counts the number of issue slots every cycle that were not consumed by the backend due to a machine clear (nuke).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x02	0x00	TOPDOWN_BAD_SPECULATION.FASTNUKE	Counts the number of issue slots every cycle that were not consumed by the backend due to Fast Nukes such as Memory Ordering Machine clears and MRN nukes.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x73	0x04	0x00	TOPDOWN_BAD_SPECULATION.MISPREDICT	Counts the number of issue slots every cycle that were not consumed by the backend due to Branch Mispredict.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x01	0x00	TOPDOWN_BE_BOUND.ALLOC_RESTRICTIONS	Counts the number of issue slots every cycle that were not consumed by the backend due to due to certain allocation restrictions.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x02	0x00	TOPDOWN_BE_BOUND.MEM_SCHEDULER	Counts the number of issue slots every cycle that were not consumed by the backend due to memory reservation stall (scheduler not being able to accept another uop).  This could be caused by RSV full or load/store buffer block.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x08	0x00	TOPDOWN_BE_BOUND.NON_MEM_SCHEDULER	Counts the number of issue slots every cycle that were not consumed by the backend due to IEC and FPC RAT stalls - which can be due to the FIQ and IEC reservation station stall (integer, FP and SIMD scheduler not being able to accept another uop).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x10	0x00	TOPDOWN_BE_BOUND.SERIALIZATION	Counts the number of issue slots every cycle that were not consumed by the backend due to IQ/JEU scoreboards or MS SCB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x20	0x00	TOPDOWN_BE_BOUND.REGISTER	Counts the number of issue slots every cycle that were not consumed by the backend due to mrbl stall.  A marble refers to a physical register file entry, also known as the physical destination (PDST).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x74	0x40	0x00	TOPDOWN_BE_BOUND.REORDER_BUFFER	Counts the number of issue slots every cycle that were not consumed by the backend due to ROB full.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x01	0x00	SERIALIZATION.IQ_JEU_SCB	Counts the number of issue slots where no uop could issue due to an IQ scoreboard that stalls allocation until a specified older uop retires or (in the case of jump scoreboard) executes. Commonly executed instructions with IQ scoreboards include LFENCE and MFENCE.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x02	0x00	SERIALIZATION.NON_C01_MS_SCB	Counts the number of issue slots not consumed by the backend due to a micro-sequencer (MS) scoreboard, which stalls the front-end from issuing from the UROM until a specified older uop retires.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x04	0x00	SERIALIZATION.C01_MS_SCB	Counts the number of issue slots in a UMWAIT or TPAUSE instruction where no uop issues due to the instruction putting the CPU into the C0.1 activity state. For Tremont, UMWAIT and TPAUSE will only put the CPU into C0.1 activity state (not C0.2 activity state).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x75	0x08	0x00	SERIALIZATION.COLOR_STALLS	Counts the number issue slots not consumed  due to a  color request for an FCW or MXCSR control register when all 4 colors (copies) are already in use.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x01	0x00	ICACHE.HIT	Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are present.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x02	0x00	ICACHE.MISSES	Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump and the instruction cache registers bytes are not present.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x80	0x03	0x00	ICACHE.ACCESSES	Counts every time the code stream enters into a new cache line by walking sequential from the previous line or being redirected by a jump.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x81	0x04	0x00	ITLB.FILLS	Counts the number of times there was an ITLB miss and a new translation was filled into the ITLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x01	0x00	ITLB_MISSES.MISS_CAUSED_WALK	Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x02	0x00	ITLB_MISSES.WALK_COMPLETED_4K	Counts the number of page walks completed due to instruction fetch misses to a 4K page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x04	0x00	ITLB_MISSES.WALK_COMPLETED_2M_4M	Counts the number of page walks completed due to instruction fetch misses to a 2M or 4M page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x08	0x00	ITLB_MISSES.WALK_COMPLETED_1G	Counts the number of page walks completed due to instruction fetch misses to a 1G page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x0e	0x00	ITLB_MISSES.WALK_COMPLETED	Counts the number of page walks completed due to instruction fetch misses to any page size.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x10	0x00	ITLB_MISSES.WALK_PENDING	Counts the number of page walks outstanding for iside in PMH every cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x20	0x00	ITLB_MISSES.STLB_HIT	Counts the number of first level TLB misses but second level hits due to an instruction fetch that did not start a page walk. Account for all pages sizes. Will result in an ITLB write from STLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x85	0x80	0x00	ITLB_MISSES.PDE_CACHE_MISS	Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0x9c	0x01	0x00	TOPDOWN_FE_BOUND.ALL_P	Counts the number of retirement slots not consumed due to front end stalls.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa4	0x02	0x00	TOPDOWN_BE_BOUND.ALL	Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL_P]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xa4	0x02	0x00	TOPDOWN_BE_BOUND.ALL_P	Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x01	0x00	FP_VINT_UOPS_EXECUTED.STD	Counts the number of uops executed on floating point and vector integer store data port.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x02	0x00	FP_VINT_UOPS_EXECUTED.P0	Counts the number of uops executed on floating point and vector integer port 0.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x04	0x00	FP_VINT_UOPS_EXECUTED.P1	Counts the number of uops executed on floating point and vector integer port 1.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x08	0x00	FP_VINT_UOPS_EXECUTED.P2	Counts the number of uops executed on floating point and vector integer port 2.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x10	0x00	FP_VINT_UOPS_EXECUTED.P3	Counts the number of uops executed on floating point and vector integer port 3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x1e	0x00	FP_VINT_UOPS_EXECUTED.PRIMARY	Counts the number of uops executed on floating point and vector integer port 0, 1, 2, 3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb2	0x1f	0x00	FP_VINT_UOPS_EXECUTED.ALL	Counts the number of uops executed on all floating point ports.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x01	0x00	INT_UOPS_EXECUTED.LD	Counts the number of uops executed on a load port.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x02	0x00	INT_UOPS_EXECUTED.STA	Counts the number of uops executed on a Store address port.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x04	0x00	INT_UOPS_EXECUTED.STD_JMP	Counts the number of uops executed on an integer store data and jump port.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x08	0x00	INT_UOPS_EXECUTED.P0	Counts the number of uops executed on integer port 0.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x10	0x00	INT_UOPS_EXECUTED.P1	Counts the number of uops executed on integer port 1.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x20	0x00	INT_UOPS_EXECUTED.P2	Counts the number of uops executed on integer port 2.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x40	0x00	INT_UOPS_EXECUTED.P3	Counts the number of uops executed on integer port 3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x78	0x00	INT_UOPS_EXECUTED.PRIMARY	Counts the number of uops executed on integer port  0,1, 2, 3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0x80	0x00	INT_UOPS_EXECUTED.2ND	Counts the number of uops executed on secondary integer ports 0,1,2,3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xb3	0xff	0x00	INT_UOPS_EXECUTED.ALL	Counts the number of uops executed on all Integer ports.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc0	0x00	0x00	INST_RETIRED.ANY_P	Counts the number of instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	2000003	0x00	0x00	1	2	0	5	0x53	0	0	1	0	0	0	0	0	0	0,1	0x00
0xc2	0x00	0x01	UOPS_RETIRED.X87	Counts the number of x87 uops retired, includes those in MS flows.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xc2	0x01	0x00	UOPS_RETIRED.EOM	Counts the number of uops retired that are the last uop of a macro-instruction.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xc2	0x02	0x00	TOPDOWN_RETIRING.ALL_P	Counts the number of consumed retirement slots.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc2	0x04	0x00	UOPS_RETIRED.MS	Counts the number of uops that are from the complex flows issued by the micro-sequencer (MS).  This includes uops from flows due to complex instructions, faults, assists, and inserted flows.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	NA	0x00
0xc2	0x08	0x00	UOPS_RETIRED.NANO_CODE	UOPS_RETIRED.NANO_CODE	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xc2	0x10	0x00	UOPS_RETIRED.DUAL_DEST	Counts the number of uops retired that were dual destination.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xc2	0x20	0x00	UOPS_RETIRED.LSD	Counts the number of uops retired that originated from a loop stream detector.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xc2	0x40	0x00	UOPS_RETIRED.FPDIV	Counts the number of floating point divide uops retired (x87 and sse, including x87 sqrt).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xc2	0x80	0x00	UOPS_RETIRED.IDIV	Counts the number of integer divide uops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xc3	0x00	0x00	MACHINE_CLEARS.ANY	Counts the total number of machine clears for any reason including, but not limited to, memory ordering, memory disambiguation, SMC, and FP assist.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x01	0x00	MACHINE_CLEARS.SMC	Counts the number of machine clears due to program modifying data (self modifying code) within 1K of a recently fetched code page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x02	0x00	MACHINE_CLEARS.MEMORY_ORDERING	Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x02	0x80	MACHINE_CLEARS.MEMORY_ORDERING_FAST	Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x04	0x00	MACHINE_CLEARS.FP_ASSIST	Counts the number of floating point operations retired that required microcode assist.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x08	0x00	MACHINE_CLEARS.DISAMBIGUATION	Counts the number of machine clears due to memory ordering in which an internal load passes an older store within the same CPU.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x08	0x80	MACHINE_CLEARS.DISAMBIGUATION_FAST	Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x10	0x00	MACHINE_CLEARS.MRN_NUKE	Counts the number of machines clears due to memory renaming.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x10	0x80	MACHINE_CLEARS.MRN_NUKE_FAST	Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x20	0x00	MACHINE_CLEARS.PAGE_FAULT	Counts the number of machine clears due to a page fault.  Counts both I-Side and D-Side (Loads/Stores) page faults.  A page fault occurs when either the page is not present, or an access violation occurs.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x40	0x00	MACHINE_CLEARS.FPC_VIRTUAL_TRAP	Counts the number of virtual traps taken.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0x80	0x00	MACHINE_CLEARS.XMC	Counts the number of machine clears due to program modifying data (cross-core modifying code) within 1K of a recently fetched code page.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc3	0xff	0x80	MACHINE_CLEARS.ANY_FAST	Counts the number of machine clears that flush the pipeline and restart the machine without the use of microcode.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc4	0x00	0x00	BR_INST_RETIRED.ALL_BRANCHES	Counts the total number of branch instructions retired for all branch types.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x00	0x01	BR_INST_RETIRED.FAR_BRANCH	Counts the number of far branch instructions retired, includes far jump, far call and return, and interrupt call and return.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x01	0x00	BR_INST_RETIRED.COND_TAKEN_BWD	Counts the number of taken backward conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x02	0x00	BR_INST_RETIRED.COND_TAKEN_FWD	Counts the number of taken forward conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x03	0x00	BR_INST_RETIRED.COND_TAKEN	Counts the number of taken conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x04	0x00	BR_INST_RETIRED.COND_NTAKEN	Counts the number of not taken conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x07	0x00	BR_INST_RETIRED.COND	Counts the number of conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x08	0x00	BR_INST_RETIRED.NEAR_RETURN	Counts the number of near RET branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x10	0x00	BR_INST_RETIRED.NEAR_INDIRECT_CALL	Counts the number of near indirect CALL branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x20	0x00	BR_INST_RETIRED.NEAR_DIRECT_CALL	Counts the number of near direct CALL branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x30	0x00	BR_INST_RETIRED.NEAR_CALL	Counts the number of near CALL branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x40	0x00	BR_INST_RETIRED.NEAR_INDIRECT_JMP	Counts the number of near indirect JMP branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x50	0x00	BR_INST_RETIRED.NEAR_INDIRECT	Counts the number of near indirect JMP and near indirect CALL branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x58	0x00	BR_INST_RETIRED.NEAR_INDIRECT_OR_RETURN	Counts the number of near indirect JMP, near indirect CALL, and RET branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0x80	0x00	BR_INST_RETIRED.NEAR_DIRECT_JMP	Counts the number of near direct JMP branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0xc0	0x00	BR_INST_RETIRED.NEAR_JMP	Counts the number of near JMP branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0xfb	0x00	BR_INST_RETIRED.NEAR_TAKEN	Counts the number of near taken branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc4	0xfb	0x01	BR_INST_RETIRED.TAKEN	Counts the total number of taken branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc5	0x00	0x00	BR_MISP_RETIRED.ALL_BRANCHES	Counts the total number of mispredicted branch instructions retired for all branch types.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc5	0x01	0x00	BR_MISP_RETIRED.COND_TAKEN_BWD	Counts the number of mispredicted taken backward conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc5	0x02	0x00	BR_MISP_RETIRED.COND_TAKEN_FWD	Counts the number of mispredicted taken forward conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc5	0x03	0x00	BR_MISP_RETIRED.COND_TAKEN	Counts the number of mispredicted taken conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc5	0x04	0x00	BR_MISP_RETIRED.COND_NTAKEN	Counts the number of mispredicted not taken conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc5	0x07	0x00	BR_MISP_RETIRED.COND	Counts the number of mispredicted conditional branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc5	0x08	0x00	BR_MISP_RETIRED.NEAR_RETURN	Counts the number of mispredicted near RET branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc5	0x10	0x00	BR_MISP_RETIRED.NEAR_INDIRECT_CALL	Counts the number of mispredicted near indirect CALL branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc5	0x40	0x00	BR_MISP_RETIRED.NEAR_INDIRECT_JMP	Counts the number of mispredicted near indirect JMP branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc5	0x50	0x00	BR_MISP_RETIRED.NEAR_INDIRECT	Counts the number of mispredicted near indirect JMP and near indirect CALL branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc5	0x58	0x00	BR_MISP_RETIRED.NEAR_INDIRECT_OR_RETURN	Counts the number of mispredicted near indirect JMP, near indirect CALL, and RET branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc5	0x5b	0x00	BR_MISP_RETIRED.NEAR_TAKEN	Counts the number of mispredicted near taken branch instructions retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	1	0	0	0,1	0x00
0xc6	0x00	0x00	FRONTEND_RETIRED.ALL	Counts the number of instructions retired that were tagged with having preceded with frontend bound behavior.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc6	0x01	0x00	FRONTEND_RETIRED.CISC	Counts the number of instructions retired that were tagged following an ms flow due to the bubble/wasted issue slot from exiting long MS flow.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc6	0x02	0x00	FRONTEND_RETIRED.BRANCH_DETECT	Counts the number of instructions retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a BAClear.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc6	0x04	0x00	FRONTEND_RETIRED.PREDECODE	Counts the number of instruction retired that are tagged after a branch instruction causes bubbles/empty issue slots due to a predecode wrong.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc6	0x08	0x00	FRONTEND_RETIRED.DECODE	Counts the number of instructions retired that were tagged every cycle the decoder is unable to send 3 uops per cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc6	0x10	0x00	FRONTEND_RETIRED.ITLB_MISS	Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc6	0x20	0x00	FRONTEND_RETIRED.ICACHE	Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to icache miss.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc6	0x40	0x00	FRONTEND_RETIRED.BRANCH_RESTEER	Counts the number of instructions retired that are tagged after a branch instruction causes bubbles /empty issue slots due to a BTClear.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc6	0x80	0x00	FRONTEND_RETIRED.OTHER	Counts the number of instructions retired tagged after a wasted issue slot if none of the previous events occurred.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc7	0x00	0x08	FP_FLOPS_RETIRED.PACKED_SP	Counts the number of retired floating point operations of packed 128 bit or 256 bit single precision instructions. Requires SW to use a multiplier of 4.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x00	0x02	FP_FLOPS_RETIRED.PACKED_HP_CMPLX4	Counts the number of retired floating point operations of packed 128 bit or 256 bit half precision complex instructions. Requires SW to use a multiplier of 32.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x00	0x01	FP_FLOPS_RETIRED.PACKED_HP_CMPLX3	Counts the number of retired floating point operations of packed 128 bit or 256 bit half precision complex instructions. Requires SW to use a multiplier of 24.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x00	0x10	FP_FLOPS_RETIRED.PACKED_DP	Counts the number of retired floating point operations of packed 128 bit or 256 bit double precision instructions. Requires SW to use a multiplier of 2.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x00	0x10	FP_FLOPS_RETIRED.SW_2X	Counts the number of retired floating point operations that require a SW multiplier of 2.  A summation of all SW multiplied events is required in order to calculate total FLOPS.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x00	0x06	FP_FLOPS_RETIRED.SW_32X	Counts the number of retired floating point operations that require a SW multiplier of 32.  A summation of all SW multiplied events is required in order to calculate total FLOPS.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x00	0x01	FP_FLOPS_RETIRED.SW_24X	Counts the number of retired floating point operations that require a SW multiplier of 24.  A summation of all SW multiplied events is required in order to calculate total FLOPS.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x00	0x50	FP_FLOPS_RETIRED.256B_PACKED_DP	Counts the number of retired floating point operations of packed 256 bit double precision instructions. Requires SW to use a multiplier of 2.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x00	0x48	FP_FLOPS_RETIRED.256B_PACKED_SP	Counts the number of retired floating point operations of packed 256 bit single precision instructions. Requires SW to use a multiplier of 4.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x00	0x90	FP_FLOPS_RETIRED.512B_PACKED_DP	Counts the number of retired floating point operations of packed 512 bit double precision instructions. Requires SW to use a multiplier of 2.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x00	0x88	FP_FLOPS_RETIRED.512B_PACKED_SP	Counts the number of retired floating point operations of packed 512 bit single precision instructions. Requires SW to use a multiplier of 4.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x01	0x00	FP_FLOPS_RETIRED.SCALAR_HP	Counts the number of retired floating point operations of scalar 16 bit half precision instructions. Requires no SW multiplier.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x02	0x00	FP_FLOPS_RETIRED.SCALAR_HP_CMPLX3	Counts the number of retired floating point operations of scalar 16 bit half precision complex instructions. Requires SW to use a multiplier of 3.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x02	0x00	FP_FLOPS_RETIRED.SW_3X	Counts the number of retired floating point operations that require a SW multiplier of 3.  A summation of all SW multiplied events is required in order to calculate total FLOPS.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x04	0x00	FP_FLOPS_RETIRED.SCALAR_HP_CMPLX4	Counts the number of retired floating point operations of scalar 16 bit half precision complex instructions. Requires SW to use a multiplier of 4 .	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x04	0x08	FP_FLOPS_RETIRED.SW_4X	Counts the number of retired floating point operations that require a SW multiplier of 4.  A summation of all SW multiplied events is required in order to calculate total FLOPS.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x08	0x00	FP_FLOPS_RETIRED.SCALAR_SP	Counts the number of retired floating point operations of scalar 32 bit single precision instructions. Requires no SW multiplier.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x10	0x00	FP_FLOPS_RETIRED.SCALAR_DP	Counts the number of retired floating point operations of scalar 64 bit double precision instructions. Requires no SW multiplier.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x19	0x00	FP_FLOPS_RETIRED.SW_1X	Counts the number of retired floating point operations that require a SW multiplier of 1.  A summation of all SW multiplied events is required in order to calculate total FLOPS.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x40	0x00	FP_FLOPS_RETIRED.PACKED_HP	Counts the number of retired floating point operations of packed 128 bit or 256 bit half precision instructions. Requires SW to use a multiplier of 8.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x40	0x00	FP_FLOPS_RETIRED.SW_8X	Counts the number of retired floating point operations that require a SW multiplier of 8.  A summation of all SW multiplied events is required in order to calculate total FLOPS.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x40	0x40	FP_FLOPS_RETIRED.256B_PACKED_HP	Counts the number of retired floating point operations of packed 256 bit half precision instructions. Requires SW to use a multiplier of 8.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x40	0x80	FP_FLOPS_RETIRED.512B_PACKED_HP	Counts the number of retired floating point operations of packed 512 bit half precision instructions. Requires SW to use a multiplier of 8.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x80	0x00	FP_FLOPS_RETIRED.PACKED_HP_DOT_PROD	Counts the number of retired floating point operations of packed 128 bit or 256 bit half precision instructions. Requires SW to use a multiplier of 16.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc7	0x80	0x00	FP_FLOPS_RETIRED.SW_16X	Counts the number of retired floating point operations that require a SW multiplier of 16.  A summation of all SW multiplied events is required in order to calculate total FLOPS.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x00	0x02	FP_ARITH_RETIRED.PACKED_HP_CMPLX4	Counts the number of retired packed 128 bit or 256 bit half precision floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x00	0x01	FP_ARITH_RETIRED.PACKED_HP_CMPLX3	Counts the number of retired packed 128 bit or 256 bit half precision floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x00	0x10	FP_ARITH_RETIRED.PACKED_DP	Counts the number of retired packed 128 bit or 256 bit double precision floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x00	0x08	FP_ARITH_RETIRED.PACKED_SP	Counts the number of retired packed 128 bit or 256 bit single precision floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x01	0x00	FP_ARITH_RETIRED.SCALAR_HP	Counts the number of retired scalar 16 bit half precision floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x02	0x00	FP_ARITH_RETIRED.SCALAR_HP_CMPLX3	Counts the number of retired scalar 16 bit half precision floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x04	0x00	FP_ARITH_RETIRED.SCALAR_HP_CMPLX4	Counts the number of retired scalar 16 bit half precision floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x08	0x00	FP_ARITH_RETIRED.SCALAR_SP	Counts the number of retired scalar 32 bit single precision floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x10	0x00	FP_ARITH_RETIRED.SCALAR_DP	Counts the number of retired scalar 64 bit double precision floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x40	0x00	FP_ARITH_RETIRED.PACKED_HP	Counts the number of retired packed 128 bit or 256 bit half precision floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0x80	0x00	FP_ARITH_RETIRED.PACKED_HP_DOT_PROD	Counts the number of retired packed 128 bit or 256 bit half precision floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0xe0	0x5f	FP_ARITH_RETIRED.256B_PACKED	Counts the number of retired packed 256 bit floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0xe0	0x9f	FP_ARITH_RETIRED.512B_PACKED	Counts the number of retired packed 512 bit floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0xe0	0x1f	FP_ARITH_RETIRED.PACKED	Counts the number of retired packed floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0xff	0x1f	FP_ARITH_RETIRED.ALL	Counts the total number of retired floating point arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc8	0xff	0x3f	FP_ARITH_RETIRED.FMA	Counts the total number of retired floating point FMA arithmetic operations.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xc9	0x02	0x00	FRONTEND_RETIRED_SOURCE.CACHE_HIT_LOCAL_CBB	Counts the number of instructions retired that were preceded by empty issue slots at allocation due to an Instruction L1 cache miss, that also missed the local L2 cache and hit an L2 in different module, L3, or MMIO, on the same CBB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc9	0x10	0x00	FRONTEND_RETIRED_SOURCE.MEM_HIT_LOCAL_SOCKET	Counts the number of instructions retired that were preceded by empty issue slots at allocation due to an Instruction L1 cache miss that hit in memory regions 0, 1, 2, 4, 5.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc9	0x3c	0x00	FRONTEND_RETIRED_SOURCE.CACHE_MISS_LOCAL_CBB	Counts the number of instructions retired that were preceded by empty issue slots at allocation due to an Instruction L1 cache miss,  that also missed the local L2 cache,  and hit in any cache, L2 or L3 or MMIO, that is not on the same CBB, or hit in Memory on the local or remote socket.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc9	0x3e	0x00	FRONTEND_RETIRED_SOURCE.L2_MISS_LOCAL_MODULE	Counts the number of instructions retired that were preceded by empty issue slots at allocation due to an Instruction L1 cache miss, that missed in the L2 cache within the same module.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc9	0x40	0x00	FRONTEND_RETIRED_SOURCE.ITLB_STLB_HIT	Counts the number of instructions retired that were tagged because empty issue slots were seen before the uop due to ITLB miss that hit in the second level TLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xc9	0x80	0x00	FRONTEND_RETIRED_SOURCE.ITLB_STLB_MISS	Counts the number of instructions retired that were preceded by empty issue slots at allocation due to an ITLB miss that also missed the second level TLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xcd	0x01	0x00	ARITH.IDIV_OCCUPANCY	Counts the number of active integer dividers per cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x01	0x00	ARITH.IDIV_ACTIVE	Counts the number of cycles when any of the integer dividers are active.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x02	0x00	ARITH.FPDIV_OCCUPANCY	Counts the number of active floating point dividers per cycle in the loop stage.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x02	0x00	ARITH.FPDIV_ACTIVE	Counts the number of cycles when any of the floating point dividers are active.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x03	0x00	ARITH.DIV_ACTIVE	Counts the number of cycles when any of the floating point or integer dividers are active.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x153	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x04	0x00	ARITH.IDIV_UOPS	Counts the number of integer divider uops executed per cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xcd	0x08	0x00	ARITH.FPDIV_UOPS	Counts the number of floating point divider uops executed per cycle.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xd0	0x11	0x00	MEM_UOPS_RETIRED.STLB_MISS_LOADS	Counts the number of load uops retired that miss in the second Level TLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd0	0x12	0x00	MEM_UOPS_RETIRED.STLB_MISS_STORES	Counts the number of store uops retired that miss in the second level TLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd0	0x13	0x00	MEM_UOPS_RETIRED.STLB_MISS	Counts the number of memory uops retired that missed in the second level TLB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd0	0x21	0x00	MEM_UOPS_RETIRED.LOCK_LOADS	Counts the number of load uops retired that performed one or more locks.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd0	0x41	0x00	MEM_UOPS_RETIRED.SPLIT_LOADS	Counts the number of retired split load uops.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd0	0x42	0x00	MEM_UOPS_RETIRED.SPLIT_STORES	Counts the number of retired split store uops.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd0	0x43	0x00	MEM_UOPS_RETIRED.SPLIT	Counts the number of memory uops retired that were splits.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd0	0x81	0x00	MEM_UOPS_RETIRED.ALL_LOADS	Counts the number of load ops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd0	0x82	0x00	MEM_UOPS_RETIRED.ALL_STORES	Counts the number of store ops retired.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd0	0x83	0x00	MEM_UOPS_RETIRED.ALL	Counts the number of memory uops retired. A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST).	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd1	0x01	0x00	MEM_LOAD_UOPS_RETIRED.L1_HIT	Counts the number of load ops retired that hit the L1 data cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd1	0x02	0x00	MEM_LOAD_UOPS_RETIRED.L1_MISS	Counts the number of load ops retired that miss in the L1 data cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd1	0x08	0x00	MEM_LOAD_UOPS_RETIRED.L2_HIT	Counts the number of load ops retired that hit in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd1	0x40	0x00	MEM_LOAD_UOPS_RETIRED.L2_MISS	Counts the number of load ops retired that miss in the L2 cache.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd3	0x01	0x00	MEM_LOAD_UOPS_RETIRED_2.CACHE_HIT_LOCAL_CBB	Counts the number of load ops retired that hit an L2 in different module, L3, or MMIO, on the same CBB.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xd3	0x08	0x00	MEM_LOAD_UOPS_RETIRED_2.MEM_HIT_LOCAL_SOCKET	Counts the number of load ops retired that hit in memory regions 0, 1, 2, 4, 5.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	1	0	0	0	0	0	0,1	0x00
0xe0	0x00	0x00	MISC_RETIRED1.WRMSR	Count the number of WRMSR instructions retired. [This event is alias to MICROCODE_RETIRED.WRMSR]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xe0	0x00	0x00	MICROCODE_RETIRED.WRMSR	Count the number of WRMSR instructions retired. [This event is alias to MISC_RETIRED1.WRMSR]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xe0	0x02	0x00	MISC_RETIRED1.LFENCE	Counts the number of LFENCE instructions retired. [This event is alias to MICROCODE_RETIRED.LFENCE]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xe0	0x02	0x00	MICROCODE_RETIRED.LFENCE	Counts the number of LFENCE instructions retired. [This event is alias to MISC_RETIRED1.LFENCE]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xe0	0xff	0x00	MISC_RETIRED1.CL_INST	Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired. [This event is alias to MICROCODE_RETIRED.CL_INST]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xe0	0xff	0x00	MICROCODE_RETIRED.CL_INST	Counts the number of CLFLUSH, CLWB, and CLDEMOTE instructions retired. [This event is alias to MISC_RETIRED1.CL_INST]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xe4	0x01	0x00	MISC_RETIRED.LBR_INSERTS	This event is deprecated. [This event is alias to LBR_INSERTS.ANY]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x01
0xe4	0x01	0x00	LBR_INSERTS.ANY	Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL. [This event is alias to MISC_RETIRED.LBR_INSERTS]	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	1	2	0	0	0x53	0	0	0	0	0	0	0	0	0	0,1	0x00
0xe6	0x01	0x00	BACLEARS.ANY	Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x02	0x00	BACLEARS.INDIRECT	Counts the number of BACLEARS due to an indirect branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x04	0x00	BACLEARS.UNCOND	Counts the number of BACLEARS due to a direct, unconditional jump.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x08	0x00	BACLEARS.RETURN	Counts the number of BACLEARS due to a return branch.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe6	0x10	0x00	BACLEARS.COND	Counts the number of BACLEARS due to a conditional jump.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0x01	0x00	MS_DECODED.MS_ENTRY	Counts the number of times entered into a ucode flow in the FEC.  Includes inserted flows due to front-end detected faults or assists.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0x02	0x00	MS_DECODED.NANO_CODE	Counts the number of times nanocode flow is executed.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
0xe7	0x04	0x00	MS_DECODED.MS_BUSY	Counts the number of cycles that the MS is busy.	0,1,2,3,4,5,6,7	0,1,2,3,4,5,6,7	1000003	0x00	0x00	0	2	0	0	0x53	0	0	0	0	0	0	0	0	0	NA	0x00
