# Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.04
# 08/31/2026 EVENT_STATUS Legend: None = 0x00, Deprecated = 0x01, Template = 0x02
# Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.
UNIT	CODE	UMASK	UMASK_EXT	NAME	DESCRIPTION	COUNTER	EVENT_STATUS	COUNTER_TYPE
iMC	0x22	0x00	0x00	UNC_M_CAS_COUNT_RD	Read CAS command sent to DRAM (including Read CAS with auto precharge)	0,1,2,3,4	0x00	PGMABLE
iMC	0x23	0x00	0x00	UNC_M_CAS_COUNT_WR	Write CAS command sent to DRAM (including Write CAS with auto precharge)	0,1,2,3,4	0x00	PGMABLE
iMC	0x3A	0x00	0x00	UNC_M_RD_DATA	This counter counts number of bytes read, in 32B chunk, per DDR channel. Counter increments by 1 after receiving 32B chunk data. Note this includes data from mode register accesses	0,1,2,3,4	0x00	PGMABLE
iMC	0x3B	0x00	0x00	UNC_M_WR_DATA	This counter counts number of bytes written, in 32B chunk, per DDR channel. Counter increments by 1 after sending 32B chunk data.	0,1,2,3,4	0x00	PGMABLE
iMC	0x3C	0x00	0x00	UNC_M_TOTAL_DATA	Total number of read and write byte transfers to/from DRAM, in 32B chunk, per DDR channel. Counter increments by 1 after sending or receiving 32B chunk data. Note this includes data from mode register accesses. Does not support channel masking	0,1,2,3,4	0x00	PGMABLE
